I.

Calendar of Events

PUBLICATIONS

237 published journal and conference papers, book chapters, and books.

Books

  • V. B. Rao, D. Overhauser, T. N. Trick, and I. N. Hajj, Switch-Level Timing Simulation of MOS VLSI Circuits, Kluwer Academic Publishers, Hingham, MA, 1989.
  • I. N. Hajj (ed.) Advances in Computer-Aided Engineering Design, JAI Press, October 1990.
  • I. N. Hajj, Computational Methods in Circuit Simulation, forthcoming.

Book Chapters

  1. I. N. Hajj and S. Skelboe, "Time-domain analysis of piecewise-linear networks," in Circuit Theory and Design, G. S. Moschytz and J. Neirynck (Eds.), Georgi: St. Saphorin, Switzerland, pp. 563-567, 1978. Also published in Proceedings of European Conference on Circuit Theory and Design, Lausanne, Switzerland, September 1978.
  2. I. N. Hajj, "Computer-Aided Circuit Analysis and Design," Handbook of Electrical and Computer Engineering, John Wiley and Sons, Inc., S.L. Chang, Editor, January 1983.
  3. I. N. Hajj, G. DeMicheli, and H. Hsieh, "Decomposition Techniques for Large-Scale Circuit Simulation," in Circuit Analysis, Simulation and Design, North-Holland Publishing Co., A. Ruehi, Editor, 1987, pp. 1-39.
  4. I. N. Hajj and S. Skelboe, "Multilevel Parallel Solver for Banded Linear Systems," in Aspects of Computation on Asynchronous Parallel Processors, M. H. Wright, Editor, Elsevier Science Publishers B.V. (North-Holland), 1989, pp. 69-78.
  5. P. Gee, M-Y. Wu, I. N. Hajj, S. M. Kang, and W. Shu, "Automatic Circuit Synthesis Using Switching Network Logic and Metal-Metal-Matrix Layout," in Advances in Computer-Aided Engineering Design, I. N. Hajj, Editor, JAI Press, 1990, pp. 57-105.
  6. S. Bobba and I. N. Hajj, “Design of Dynamic Circuits with Enhanced Noise Tolerance,” in Signal Integrity Effects in Custom IC and ASIC Design, Raminderpal Singh, Editor, IEEE Press and Wiley Interscience, 2002, pp. 137-142. Also appeared in Proceedings of the ASIC/SOC Conference, September 1999.
  7. G. Bai, S. Bobba, and I. N. Hajj, “Simulation and Optimization of the Power Distribution in VLSI Circuits,” in Signal Integrity Effects in Custom IC and ASIC Design, Raminderpal Singh, Editor, IEEE Press and Wiley Interscience, 2002, pp. 291-296. Also appeared in Proceedings of the International Conference on Computer Aided Design, November 2000.
     


Journal Publications

  1. E. S. Kuh and I. N. Hajj, "Nonlinear circuit theory: resistive networks," Proceedings of the IEEE, Vol. 59, pp. 340-355, March 1971.
  2. I. N. Hajj, "Updating method for LU factorization," Electronics Letters, Vol. 8, no. 7, pp. 186-188, April 1972.
  3. I. N. Hajj, D. J. Roulston, and P. R. Bryant, "Efficient analysis of transistor circuits from device fabrication data," Proceedings of the IEEE, Vol. 62, no. 3, pp. 408-410, March 1974.
  4. I. N. Hajj, D. J. Roulston, and P. R. Bryant, "A three-terminal piecewise-linear modeling approach to dc analysis of transistor circuits," Circuit Theory and Applications, Vol. 2, pp. 133-147, June 1974.
  5. I. N. Hajj, "Computation of Thevenin and Norton equivalents," Electronics Letters, Vol. 12, no. 11, pp. 273-274, May 1976.
  6. I. N. Hajj, "Computation of group delay, and its sensitivities," Electronics Letters, Vol. 12, no. 13, pp. 336-337, June 1976.
  7. I. N. Hajj, D. J. Roulston, and P. R. Bryant, "Generation of transient response of nonlinear bipolar transistor circuits from device fabrication data," IEEE Journal of Solid-State Circuits, Vol. SC-12, no. 1, pp. 29-38, February 1977.
  8. I. N. Hajj, "Solution of interconnected subsystems," Electronics Letters, Vol. 13, no. 3, pp. 78-79, February 1977.
  9. I. N. Hajj, "Computation of hybrid equations of linear multiports," IEEE Transactions on Circuits and Systems, Vol. CAS-24, no. 11, pp. 655-656, November 1977.
  10. D. J. Roulston, N. G. Chamberlain, P. R. Bryant, I. N. Hajj, and P. Dufond, "Computer-aided analysis of nonlinear JFET amplifiers from device fabrication data,"  IEEE Journal of Solid-State Circuits, Vol. SC-13, no. 2, pp. 266-268, April 1978.
  11. I. N. Hajj, "Formulation of multiport equations via block matrix elimination," Proceedings of the IEEE (Letters), Vol. 66, no. 10, pp. 1275-1277, October 1978.
  12. I. N. Hajj, D. J. Roulston, P. R. Bryant, and M. Vlach, "Generation and sensitivity of input-output dc plots using interactive computing," Computer-Aided Design, IPC Science and Tech. Press, England, Vol. 11, pp. 37-39, January 1979.
  13. I. N. Hajj and S. Skelboe, "Time-domain analysis of nonlinear systems with finite number of continuous derivatives," IEEE Transactions on Circuits and Systems, Vol. CAS-26, pp. 297-303, May 1979.
  14. I. N. Hajj, "Sparsity considerations in network solution by tearing," IEEE Transactions on Circuits and Systems, Vol. CAS-27, no. 5, pp. 357-366, May 1980.
  15. I. N. Hajj, "Algorithms for solution updating due to large changes in system parameters," International Journal on Circuit Theory and Applications, Vol. 9, pp. 1-14, January 1981.
  16. I. N. Hajj and S. Skelboe, "Steady-state analysis of piecewise-linear dynamic systems," IEEE Transactions on Circuits and Systems, Vol. CAS-28, no. 3, pp. 234-242, March 1981.
  17. I. N. Hajj, P. Yang, and T. N. Trick, "Avoiding zero pivots in the modified nodal approach," IEEE Transactions on Circuits and Systems, Vol. CAS-28, no. 4, pp. 271-279, April 1981.
  18. P. Sauer, I. N. Hajj, M. A. Pai, and T. N. Trick, "Computer methods in electric network analysis," IEEE Winter Power Meeting, February 1983, and IEEE Transactions on Power Apparatus and Systems, Vol. PAS-102 pp. 1726-1731, June 1983.
  19. I. N. Hajj, "A note on a theorem on the summation of driving-point and transfer network impedances," Proceedings of the IEEE (Letters), pp. 395-396, February 1984.
  20. I. N. Hajj and D. Saab, "Switch-level logic simulation of digital bipolar circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-6, no. 2, pp. 251-258, March 1987.
  21. T. K. Yu, S. M. Kang, I. N. Hajj, and T. N. Trick, "Statistical performance modeling and parametric yield estimation of MOS VLSI," IEEE Transactions on Computer-Aided Design, Vol. CAD-6, no. 6, pp. 1013-1022, November 1987.
  22. O. Tejayadi and I. N. Hajj, "Dynamic partitioning method for piecewise-linear VLSI circuit simulation," International Journal on Circuit Theory and Applications, Special Issue of Fundamental Methods in Computer-Aided Circuit Design, pp. 457-472, October 1988.
  23. M. Desai and I. N. Hajj, "On the convergence of block time-point relaxation methods for circuit simulation," IEEE Transactions on Circuits and Systems, Vol. 36, no. 7, pp. 948-958, July 1989.
  24. M. Y. Wu and I. N. Hajj, "Switching network logic approach to sequential MOS circuit design," IEEE Transactions on Computer-Aided Design, Vol. 8, no. 7, pp. 782-794, July 1989.
  25. R. Saleh, K. Gallivan, M-C. Chang, I. N. Hajj, D. Smart, and T. N. Trick, "Parallel circuit simulation on supercomputers," Proceedings of the IEEE, Vol. 77, no. 12, pp. 1915-1931, December 1989.
  26. P. Gee, M. Y. Wu, S. M. Kang, and I. N. Hajj, "A metal-metal cell generator for multi-level technology," Integration, the VLSI Journal, Vol. 9, no. 1, pp. 25-47, February 1990.
  27. F. Najm, R. Burch, P. Yang, and I. N. Hajj, "Probabilistic simulation for reliability analysis of CMOS VLSI circuits," IEEE Transactions on Computer-Aided Design, Vol. 9, no. 4, pp. 439-450, April 1990. (Best Paper Award)
  28. F. Najm and I. N. Hajj, "The complexity of fault detection in MOS VLSI circuits," IEEE Transactions on Computer-Aided Design, Vol. 9, no. 9, pp. 995-1001, September 1990.
  29. P. Gee, M. Y. Wu, S. M. Kang, and I. N. Hajj, "Automation synthesis of metal-metal matrix layout for double-metal VLSI," International Journal of Computer-Aided Design, Vol. 2, no. 1, pp. 83-104, 1990.
  30. I. N. Hajj, and S. Skelboe, "A multilevel parallel solver for block tridiagonal and banded systems," Parallel Computing, Elsevier, Vol. 15, pp. 21-45, 1990.
  31. F. N. Najm, I. N. Hajj, and P. Yang, "An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits," IEEE Transactions on Computer-Aided Design, Vol. 10, no. 11, pp.  1372-1381, November 1991.
  32. T. Yang, Y.-H. Chang, D. G. Saab, and I. N. Hajj, "Switch-level timing simulation of bipolar ECL circuits," IEEE Transactions on Computer-Aided Design,  Vol. 12, no. 4, pp. 516-530, April 1993.
  33. P. Y. Chung, Y.-M. Wang, and I. N. Hajj, "Diagnosis and correction of logic design errors in digital circuits," IEEE Transactions on VLSI Systems, Vol. 2, no. 3, pp. 320-332, September 1994.
  34. P.-C. Li, G. I. Stamoulis, and I. N. Hajj, "A probabilistic timing approach to hot-carrier effect estimation," IEEE Transactions on Computer-Aided Design,  Vol. 13, no. 10, pp. 1223-1234, October 1994. 
  35. W.-T. Chuang, S. S. Sapatnekar, and I. N. Hajj, "Timing and area optimization for standard-cell VLSI circuit design," IEEE Transactions on Computer-Aided Design, Vol. 14, no. 3, pp. 308-320, March 1995.
  36. T. Lee, W. T. Chuang, I. N. Hajj, and W. K. Fuchs, "Circuit-level dictionaries of CMOS bridging faults," IEEE Transactions on Computer-Aided Design, Vol. 14, no. 5, pp. 596-603, May 1995.
  37. H. Kriplani, F. Najm, and I. N. Hajj, "Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: algorithms, signal correlations, and their resolution," IEEE Transactions on Computer-Aided Design,  Vol. 14, no. 8, pp. 998-1012, August 1995.
  38. P.-C. Li and I. N. Hajj, "Computer-aided redesign of VLSI circuits for hot-carrier reliability," IEEE Transactions on Computer-Aided Design, Vol. 15, no. 5, pp. 453-464, May 1996.
  39. P. Y. Chung and I. N. Hajj, "Diagnosis and correction of multiple design errors in digital circuits," IEEE Transactions on VLSI Systems, Vol. 5, no. 2, pp. 233-237, June 1997.\
  40. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "Analytical estimation of signal transition activity from word-level statistics," IEEE Transactions on Computer-Aided Design, Vol. 16, no. 7, pp. 718-733, July 1997.
  41. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "A coding framework for low-power address and data busses," IEEE Transactions on VLSI Systems,  Vol. 7, no. 2, pp. 212-221, June 1999.
  42. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "Decorrelating (DECOR) transformations for low-power digital filters," IEEE Transactions on Circuits and Systems, II, Vol. 46, no. 6, pp. 776-788, June 1999.
  43. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "Signal coding for low power: fundamental limits and practical realizations," IEEE Transactions on Circuits and Systems, II, Vol. 46, no. 7, pp. 923-929, July 1999.
  44. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "Information-theoretic bounds on average signal transition activity," IEEE Transactions on VLSI Systems,  Vol. 7, no. 3, pp. 359-368, September 1999.
  45. A. Veneris and I. N. Hajj, "Design error diagnosis and correction via test vector simulation," IEEE Transactions on Computer-Aided Design,  Vol. 18, no. 12, pp. 1803-1816, December 1999.
  46. N. Bellas, I. N. Hajj, C. Polychronopoulos, and George Stamoulis, "Architectural and techniques for energy reduction in the high performance microprocessors," IEEE Transactions on VLSI Systems, Vol. 8, no. 3, pp. 317-326, June 2000.
  47. N. Bellas, I. N. Hajj, and C. Polychronopoulos, "Using dynamic cache management techniques to reduce energy in general purpose processors," IEEE Transactions on VLSI Systems, Vol. 8, Issue 6, pp. 693-708, December 2000.
  48. S. Ramprasad, I. N. Hajj, and F. N. Najm, "An optimization technique for dual-output domino logic," IEEE Transactions on VLSI Systems, Vol. 10, Issue 4, pp. 508-511, August 2002.
  49. M. R. Becer, D. Blaauw,  P. Panda and I. N. Hajj, “Early probabilistic noise estimation for capacitively coupled interconnects,” IEEE Transactions On Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, no. 3, pp. 337-345, March 2003.
  50. M. R. Becer, D. Blaauw, I. Algor, R. Panda, C. Oh, V. Zolotov and I. N. Hajj, “Post-route gate sizing for crosstalk noise reduction,” IEEE Transactions On Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, no. 12, pp.1670-1677, December 2004.
  51. I. N. Hajj, “Extended Nodal Analysis,” IEEE Transactions On Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions On Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, no. 1, pp. 89-100, January 2012.
  52. I. N. Hajj, “On Device Modeling for Circuit Simulation With Application to Carbon-Nanotube and Graphene Nano-Ribbon Field-Effect Transistors,” IEEE Transactions On Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, no. 3, pp. 495-499, March 2015.

Conference Publications

  1. I. N. Hajj, "Computer analysis of piecewise-linear resistive networks," Summer School on Circuit Theory, Tale, Czechoslovakia, September 1971.
  2. I. N. Hajj, D. J. Roulston, and P. R. Bryant, "DC analysis of transistor circuits via a three-terminal piecewise-linear modeling approach," IEEE International Symposium on Circuit Theory, Toronto, Ontario, Canada, April 1973.
  3. I. N. Hajj, K. Singhal, J. Vlach, and P. R. Bryant, "WATAND – a program for the analysis and design of linear and piecewise-linear networks," Proceedings of IEEE 16th Midwest Symposium on Circuit Theory, Waterloo, Ontario, Canada, April 1973.
  4. I. N. Hajj, K. Singhal, and J. Vlach, "Efficient analysis of nonlinear networks by piecewise-linear approximation," Proceedings of 11th Allerton Conference on Circuit Theory, Champaign, IL, October 1973.
  5. I. N. Hajj, "Computer simulation of electrical networks," 5th Science Meeting of the Lebanese Association for the Advancement of Science, Beirut, Lebanon, December 1973.
  6. I. N. Hajj, "Some results in the analysis of nonlinear systems by piecewise-linearization," 6th Science Meeting of the Lebanese Association for the Advancement of Science, Beirut, Lebanon, December 1974.
  7. I. N. Hajj, D. J. Roulston, and P. R. Bryant, "Nonlinear analysis of transistor circuits from device fabrication data," Proceeding of the European Conference on Circuit Theory and Design, Genoa, Italy, September 1976, pp. 507-514.
  8. I. N. Hajj, "Sparse matrix algorithms for diakoptic analysis," Proceedings of IEEE Ninth Ann. Southeastern Symposium on System Theory, Charlotte, NC, March 1977, pp. 1-10.
  9. I. N. Hajj and K. Singhal, "Piecewise-linear analysis and large-change sensitivity computation by solution of modified systems," Proceedings of IEEE 1977 International Symposium Circuits and Systems, Phoenix, AZ, April 1977, pp. 60-63.
  10. I. N. Hajj, "Sparsity considerations in network solution by tearing," Proceedings of IEEE International Symposium on Circuits and Systems, New York, NY, May 1978, pp. 170-174.
  11. I. N. Hajj, "Diakoptics and block elimination," IEEE Power Engineering Society Summer Meeting, Los Angeles, CA, July 1978, paper A78, pp. 564-567.
  12. I. N. Hajj and S. Skelboe, "Time-domain analysis of piecewise-linear networks," Proceedings of European Conference on Circuit Theory and Design, Lausanne, Switzerland, September 1978; also published in Circuit Theory and Design, G. S. Moschytz and J. Neirynck (Eds.), Georgi: St. Saphorin, Switzerland, pp. 563-567, 1978.
  13. P. R. Bryant, I. N. Hajj, and M. Vlach, "Interactive circuit simulation: the user oriented program WATAND," Proceedings of 4th International Symposium on Computers, Electronics and Control, Toronto, Ontario, Canada, November 1978. (Invited)
  14. I. N. Hajj, "Large-change sensitivity computation and partitioning," Proceedings of IEEE 22nd Midwest Symposium on Circuits and Systems, Philadelphia, PA, June 1979, pp. 216-219.
  15. I. N. Hajj, D. J. Roulston, and P. R. Bryant, "Computer-aided design and evaluation of bipolar transistors and circuits for high efficiency microwave power conversion," SPACECAD '79 Symposium, Bologna, Italy, September 1979, pp. 177-187.
  16. P. Yang, I. N. Hajj, and T. N. Trick, "On equation ordering in the modified nodal approach," Proceedings of IEEE 13th Asilomar Conference on Circuits and Systems, Pacific Grove, CA, November 1979, pp. 112-116.
  17. I. N. Hajj, P. Yang, and T. N. Trick, "Avoiding zero pivots in the modified nodal approach," Proceedings of IEEE 1980 International Symposium on Circuits and Systems, Houston, TX, April 1980, pp. 833-835.
  18. I. N. Hajj and S. Skelboe, "Solution trajectories in piecewise-linear dynamic systems," Proceedings of IEEE International Symposium on Circuits and Systems, Houston, TX, April 1980, pp. 905-908. (Invited)
  19. I. N. Hajj and S. Skelboe, "Steady-state analysis of piecewise-linear circuits", Proceedings of 1980 European Conference on Circuit Theory and Design, Warsaw, Poland, September 1980.
  20. P. Yang, I. N. Hajj, and T. N. Trick, "SLATE: a circuit simulator program with latency exploitation and node tearing," Proceedings of IEEE International Conference on Circuits and Computers, Port Chester, NY, October 1980.
  21. I. N. Hajj, "An updating algorithm for the shortest path problem," Proceedings of IEEE 1981 International Symposium on Circuits and Systems, Chicago, IL, April 1981, pp. 802-805.
  22. I. N. Hajj, "Large-charge sensitivity of large-scale networks," Proceedings of IEEE 24th Midwest Symposium on Circuits and Systems, Albuquerque, NM, June 1981, pp. 227-229.
  23. P. Yang, I. N. Hajj, and T. N. Trick, "Tearing and multi-level exploitation of latency in a circuit simulation program," Proceedings of 1981 European Conference on Circuit Theory and Design, The Hague, The Netherlands, August 1981, pp. 157-163.
  24. I. N. Hajj, "Decomposition algorithms for the shortest path problem," Proceedings of 1982 IEEE Symposium on Circuits and Systems, Rome, Italy, May 1982, pp. 975-978.
  25. D. Saab and I. N. Hajj, "A logic expression generator for MOS circuits," Proceedings of 1982 IEEE Int. Conf. on Circuits and Computers (ICCC), New York, NY, September 29-October 1, 1982, pp. 328-331.
  26. Y. P. Wei, I. N. Hajj, and T. N. Trick, "A prediction-relaxation-based simulator for MOS circuits," Proceedings of 1982 IEEE International Conference On Circuits and Computers (ICCC), New York, NY, September 29-October 1, 1982, pp. 34-37.
  27. I. N. Hajj and D. Saab, "Symbolic logic simulation of MOS circuits," Proceedings of IEEE International Symposium on Circuits and Systems, Newport Beach, CA, May 2-4, 1983, pp. 246-249.
  28. P. Sauer, I. N. Hajj, M. A. Pai, and T. N. Trick, "Computer methods in electric network analysis," IEEE Winter Power Meeting, February 1983, and IEEE Trans. on Power Apparatus and Systems, Vol. PAS-102 pp. 1726-1731, June 1983.
  29. W. K. Chia, I. N. Hajj, and T. N. Trick, "A survey of relaxation methods for the simulation of digital integrated circuits," Proceedings of IEEE 26th Symposium on Circuits and Systems, Hollywood, CA, August 15-16, 1983, pp. 360-363.
  30. I. N. Hajj and D. Saab, "Fault modeling and logic simulation of MOS VLSI circuits based on logic expression extraction," Proceedings of IEEE International Conference on Computer-Aided Design, Santa Clara, CA, September 1983, pp. 99-100.
  31. V. B. Rao, T. N. Trick, and I. N. Hajj, "A table-driven delay-operator approach to timing simulation of MOS VLSI circuits," Proceedings of IEEE International Conference on Computer Design: VLSI in Computers, Port Chester, NY, November 1983, pp. 445-448.
  32. W. K. Chia, T. N. Trick, and I. N. Hajj, "Stability and convergence properties of relaxation methods for hierarchical simulation of VLSI circuits," Proceedings of IEEE International Symposium on Circuits and Systems, Montreal, Canada, May 7-10, 1984, pp. 848-851.
  33. I. N. Hajj and K. Jung, "A piecewise-linear approach to timing analysis of VLSI circuits," Proceedings of IEEE International Symposium on Circuits and Systems, Montreal, Canada, May 7-10, 1984, pp. 1443-1446.
  34. L.-G. Mao and I. N. Hajj, "A piecewise-linear approach to dc analysis of large-scale integrated circuits," Fifth International Symposium on Network Theory, Sarajevo, Yugoslavia, September 1984, pp. 472-476.
  35. D. Saab and I. N. Hajj, "Parallel and concurrent fault simulation of MOS circuits," Proceedings of IEEE International Conference on Computer Design (ICCD'84), Port Chester, NY, October 1984, pp. 752-756.
  36. I. N. Hajj, D. Saab, and B. Rosario, "Logic and timing simulation of bipolar ECL circuits," Proceedings of IEEE International Conference on Computer-Aided Design (ICCAD-84), Santa Clara, CA, November 1984, pp. 194-196.
  37. I. N. Hajj and D. Saab, "On the functional logic simulation of digital transistor circuits," Proceedings of IEEE International Symposium on Circuits and Systems, Kyoto, Japan, June 1985, pp. 1281-1284.
  38. L.-G. Mao and I. N. Hajj, "A Gauss-Seidel piecewise-linear method for the analysis of large-scale integrated circuits," International Conference on Circuits and Systems, Beijing, China, June 1985, pp. 420-422.
  39. W. K. Chia, T. N. Trick, and I. N. Hajj, "Implementation of a relaxation technique in a general purpose circuit simulator," Proceedings of IEEE 1985 International Conference on Circuits and Systems, Beijing, China, June 1985, pp. 423-426.
  40. I. N. Hajj, "A path algebra for switch-level simulation," Proceedings of IEEE International Conference on Computer-Aided Design, Santa Clara, CA, November 1985, pp. 153-155.
  41. D. Overhauser, I. N. Hajj, and V. R. Rao, "Switch-level timing analysis of VLSI MOS circuits," Proceedings of IEEE International Symposium On Circuits and Systems, San Jose, CA, May 1986, pp. 761-764.
  42. J. Stein, D. G. Saab, and I. N. Hajj, "A special-purpose architecture for concurrent fault simulation," Proceedings of IEEE International Conference on Computer Design (ICCD '86), Port Chester, NY, October 1986.
  43. T. K. Yu, S. M. Kang, I. N. Hajj, and T. N. Trick, "Statistical modeling of VLSI circuit performances," Proceedings of IEEE International Conference on Computer-Aided Design (ICCAD '86), Santa Clara, CA, November 1986, pp. 224-227.
  44. M. P. Desai and I. N. Hajj, "Block time-point relaxation algorithms for circuit simulation," Proceedings of IEEE Int. Conf. on Computer-Aided Design (ICCAD'86), Santa Clara, CA, November 1986, pp. 88-91.
  45. I. N. Hajj and F. Najm, "Test generation for physical faults in MOS VLSI circuits," Proceedings of COMP-EURO '87: VLSI and Computer, Hamburg, Germany, May 1987, pp. 386-389.
  46. O. Tejayadi and I. N. Hajj, "Dynamic partitioning method for precise-linear MOS design," Proceedings of IEEE International Conference on Computer-Aided Design, Santa Clara, CA, November 1987, pp. 102-105.
  47. M. Y. Wu and I. N. Hajj, "Modified sequential CMOS circuit design," Proceedings of IEEE International Conference on Computer-Aided Design, Santa Clara, CA, November 1987, pp. 460-463.
  48. P. Gee, M. Y. Wu, S. M. Kang, and I. N. Hajj, "Metal-metal matrix M3 CMOS cell generator with compaction," Proceedings of IEEE International Conference on Computer-Aided Design, Santa Clara, CA, November 1987, pp. 184-187.
  49. I. N. Hajj and S. Skelboe, "A multilevel parallel solver for banded linear systems," 12th Biennial Conference on Numerical Analysis, Dundee Scotland, June 1987; also presented at The Third Conference on Hypercube Concurrent Computers and Applications, Pasadena, CA, January 1988.
  50. D. Overhauser and I. N. Hajj, "Multilevel circuit partitioning for switch-level timing simulation," Proceedings of IEEE International Symposium On Circuits and Systems, Espoo, Finland, June 1988, pp. 1361-1364.
  51. D. G. Saab, A. T. Yang, and I. N. Hajj, "Delay modeling and timing of bipolar digital circuits," Proceedings of IEEE 25th Design Automation Conference (DAC), Anaheim, CA, June 1988, pp. 288-293.
  52. I. N. Hajj and S. Skelboe, "A multilevel solver for banded linear systems," Proceedings of International Federation for Information Processing (IFIP) Conference, Stanford, CA, August 1988.
  53. P. Gee, I. N. Hajj, and S. M. Kang, "iSILVER: A symbolic layout generator for MOS circuits," Proceedings of IEEE 31st Midwest Symposium On Circuits and Systems, Rolla, MO, August 1988, pp. 142-145.
  54. D. Overhauser and I. N. Hajj, "A tabular macromodeling approach to fast timing simulation including parasitics," Proceedings of IEEE International Conference on Computer-Aided Design (ICCAD-88), Santa Clara, CA, November 1988, pp. 70-73.
  55. M.-C. Chang and I. N. Hajj, "PRIDE: a parallel integrated circuit simulator using direct method," Proceedings of IEEE International Conference on Computer-Aided Design (ICCAD-88), Santa Clara, CA, November 1988, pp. 304-307.
  56. F. Najm, R. Burch, P. Yang, and I. N. Hajj, "CREST-a current estimator for CMOS circuits," Proceedings of IEEE International Conference on Computer-Aided Design (ICCAD-88), Santa Clara, CA, November 1988, pp. 204-207.
  57. T. K. Yu, S. M. Kang, I. N. Hajj, and T. N. Trick, "EDISON: an interactive statistical design tool for MOS VLSI circuits," Proceedings of IEEE International Conference on Computer-Aided Design (ICCAD-88), Santa Clara, CA, November 1988, pp. 20-23.
  58. M-C. Chang and I. N. Hajj, "Parallel solution of sparse linear systems by exploiting independent pivots," Proceedings of International Computer Symposium '88, Taipei, Taiwan, December 1988, pp. 434-439.
  59. I. N. Hajj and O. Tejayadi, "Parallel solution of piecewise-linear transistor circuits," Proceedings of IEEE International Symposium on Circuits and Systems, Portland, OR, May 1989, pp. 681-684.
  60. F. Najm, I. Hajj, and P. Yang, "Electromigration median time-to-failure based on a stochastic current waveform," Proceedings of IEEE International Conference on Computer Design (ICCD '89), Cambridge, MA, October 1989, pp. 447-450.
  61. D. Saab, I. N. Hajj, and J. Rahmeh, "Parallel-concurrent fault simulation," Proceedings of IEEE International Conference on Computer Design (ICCD'89), Cambridge, MA, October 1989, pp. 298-301.
  62. D. Overhauser and I. N. Hajj, "Feedback processing in fast timing simulation on a multiprocessor system," Proceedings of IEEE 32nd Midwest Symposium on Circuits and Systems, Champaign, IL, August 1989, pp. 466-469.
  63. P. Gee, I. N. Hajj, and S. M. Kang, "An improved min-cut approach for gate matrix and metal-metal matrix circuit layout," Proceedings of IEEE 32nd Midwest Symposium on Circuits and Systems, Champaign, IL, August 1989, pp. 555-558.
  64. I. N. Hajj, S. M. Kang, and P. Gee, "Automatic circuit synthesis for multilevel metal MOS technology," Proceedings of IEEE International Conference on VLSI and CAD, Seoul, Korea, October 17-20, 1989, pp. 149-153.
  65. D. Overhauser, I. N. Hajj, and Y.-F. Hsu, "Automatic mixed-mode timing simulation," Proceedings of IEEE International Conference on Computer-Aided Design (ICCAD-89), Santa Clara, CA, November 1989, pp. 84-87.
  66. F. Najm, I. N. Hajj, and P. Yang, "Computation of bus current variance for reliability estimation of VLSI circuits," Proceedings of IEEE International Conference on Computer-Aided Design (ICCAD-89), Santa Clara, CA, November 1989, pp. 202-205.
  67. P. Gee, I. N. Hajj, and S. M. Kang, "A custom cell generation system for double metal CMOS technology," Proceedings of IEEE International Conference on Computer-Aided Design (ICCAD-89), Santa Clara, CA, November 1989, pp. 140-143.
  68. P.-Y. Chung and I. N. Hajj, "Parallel solution of sparse linear systems on a vector multiprocessor computer," Proceedings of IEEE International Symposium on Circuits and Systems, New Orleans, LA, May 1-3, 1990, pp. 1577-1580.
  69. D. Overhauser and I. N. Hajj, "iDSIM2: an environment for mixed-mode simulation," Proceedings of IEEE Custom Integrated Circuits Conference, Boston, MA, May 13-16, 1990, pp. 5.2.1-5.2.4.
  70. F. N. Najm and I. N. Hajj, "Probabilistic simulation of VLSI circuits and systems," 1990 Bilkent International Conference on New Trends in Communications, Control and Signal Processing, Ankara, Turkey, July\02-5, 1990, pp. 1114-1117. (Invited)
  71. H.-Y. Jun and I. N. Hajj, "An efficient timing simulation approach for MOS digital circuits," Proceedings of IEEE 33rd Midwest Symposium on Circuits and Systems, Calgary, Alberta, Canada, August 1990, pp 235-238.
  72. H.-Y. Jun, I. N. Hajj, S.-H. Lee, and S.-B. Park, "High-speed VLSI logic simulation using bit-wise operations and parallel processing," Proceedings of IEEE International Conference on Computer Design, Boston, MA, September 1990, pp. 171-174.
  73. T. N. Trick, I. N. Hajj, and R. Saleh, ""Circuit simulation on multiprocessors," URSI Meeting, Prague, Czechoslovakia, September 1990. (Invited)
  74. I. N. Hajj, "An algebra for switch-level simulation," Proceeding of IEEE International Conference on Computer-Aided Design, Santa Clara, CA, November 1990, pp. 488-491.
  75. I. N. Hajj, V. B. Rao, R. Iimura, H. Cha, and R. Burch, "A system for electromigration analysis in VLSI metal patterns," Proceedings of IEEE Custom Integrated Circuits Conference, San Diego, CA, May 12-15, 1991, pp. 4.4.1-4.4.4.
  76. Y. Leblebici, P. C. Li, S. M. Kang, and I. N. Hajj, "Hierarchical simulation of hot-carrier induced damages in VLSI circuits," Proceedings of IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1991, pp. 29.3.1-29.3.4.
  77. Y.-H. Jun and I. N. Hajj, "A mixed-mode simulator for digital/analog VLSI circuits using efficient timing simulation approach," Proceedings Of IEEE International Symposium on Circuits and Systems, Singapore, June 1991, pp. 2383-2386.
  78. I. N. Hajj, "A circuit-based approach to switch-level simulation," European Conference on Circuit Theory and Design, Copenhagen, Denmark, September 1991, pp. 274-283.
  79. T. P.-C. Lee and I. N. Hajj, "A switch-level matrix approach to transistor-level fault simulation," Proceedings of IEEE International Conference on Computer-Aided Design (ICCAD-91), Santa Clara, CA, November 1991, pp. 554-557. (Best Paper in Testing Area)
  80. I. N. Hajj and T. Lee, "Simulation of physical faults in VLSI circuits," Proceedings of IEEE 10th VLSI Test Symp.'92, Atlantic City, NJ, April 1992, pp. 202-207.
  81. H. Kriplani and I. N. Hajj, "Calculation of average and variance bus currents for reliability analysis of VLSI CMOS circuits," Proceedings of IEEE International Symposium on Circuits and Systems, San Diego, CA, May 1992, pp. 371-374.
  82. L. Brauer and I. N. Hajj, "An algorithm to identify voltage regulators in ECL circuits," Proceedings of IEEE International Symposium on Circuits and Systems, San Diego, CA, May 1992, pp. 2101-2103.
  83. H. Kriplani, F. Najm, and I. N. Hajj, "Maximum current estimation in CMOS circuits," Proceedings of 29th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, June 1992, pp. 2-7. (Nominated for Best Paper Award)
  84. I. N. Hajj, "Computational techniques for circuit analysis and design," Tutorial, VII Microelectronics Brazilian Congress, São Paulo, Brazil, July 1992. (Invited)
  85. I. N. Hajj, "Logic and fault simulation of VLSI MOS circuits," VII Microelectronic Brazilian Congress, São Paulo, Brazil, July 1992. (Invited)
  86. I. N. Hajj, "Microelectronics and nanoelectronics," First Congress of Arab Scientists and Technologists Abroad, Amman, Jordan, August 1992. (Invited)
  87. P. Y. Chung and I. N. Hajj, "ACCORD: automatic catching and correction of logic design errors," Proceedings of IEEE International Test Conference '92, Baltimore, MD, September 1992, pp. 742-751.
  88. P. C. Li, G. I. Stamoulis, and I. N. Hajj, "A probabilistic timing approach to hot-carrier effect estimation," Proceedings of IEEE International Conference on Computer-Aided Design (ICCAD-92), Santa Clara, CA, November 1992, pp. 210-213.
  89. W. Chuang and I. N. Hajj, "Mixed-mode simulation for accurate MOS bridging fault detection," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS-93), Chicago, IL, May 1993, pp. 1503-1506.
  90. P. Y. Chung, I. N. Hajj, and J. H. Patel, "Efficient variable ordering heuristics for shared ROBDD," Proceedings of IEEE International Symposium On Circuits and Systems (ISCAS-93), Chicago, IL, May 1993, pp. 1690-1693.
  91. W. Chuang, S. S. Sapatnekar, and I. N. Hajj, "Delay and area optimization for discrete gate sizes under double-sided timing constraints," Proceedings of IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1993, pp. 9.4.1-9.4.4.
  92. H. Kriplani, F. Najm, P. Yang, and I. N. Hajj, "Resolving signal correlations for estimating maximum currents in CMOS combinational circuits," Procedings of 30th ACM/IEEE Design Automation Conference (DAC), Dallas, TX, June 1993, pp. 384-388. (Nominated for Best Paper Award)
  93. G. Stamoulis and I. N. Hajj, "Improved techniques for probabilistic simulation including signal correlation effects," Proceedings of 30th ACM/IEEE Design Automation Conference (DAC), Dallas, TX, June 1993, pp. 379-383.
  94. P. Y. Chung, Y. M. Wang, and I. N. Hajj, "Diagnosis and correction of logic design errors in digital circuits," Proceedings of 30th ACM/IEEE Design Automation Conference (DAC), Dallas, TX, June 1993, pp. 503-508.
  95. P.-C. Li and I. N. Hajj, "Computer-aided redesign of VLSI circuits for hot-carrier reliability," Proceedings of IEEE International Conference on Computer Design (ICCD'93), Cambridge, MA, October 1993, pp. 534-537.
  96. H. Kriplani, F. Najm, and I. N. Hajj, "Worst-case voltage drops in power and ground buses of CMOS VLSI circuits," TECHCON'93, Atlanta, GA, September 1993, pp. 402-404.
  97. P. Y. Chung and I. N. Hajj, "Logic design error diagnosis and correction," TECHCON'93, Atlanta, GA, September 1993, p. 496.
  98. W.-T. Chuang, S. S. Sapatnekar, and I. N. Hajj, "A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area," Proceedings of IEEE International Conference on Computer-Aided Dessign (ICCAD'93), Santa Clara, CA, November 1993, pp. 220-223.
  99. T. Lee, W.-T. Chuang, I. N. Hajj, and W. K. Fuchs, "Circuit-level dictionaries of CMOS bridging faults," Proceedings of 12th IEEE VLSI Test Symposium, Cherry Hill, NJ, April 1994, pp. 386-389.
  100. P.-C. Li, G. I. Stamoulis, and I. N. Hajj, "Probe-d: a hot-carrier and oxide reliability simulator," Proceedings of IEEE International Reliability Physics Symposium, San Jose, CA, April 1994, pp. 274-279.
  101. G. I. Stamoulis and I. N. Hajj, "Slope considerations in probabilistic simulation," Proceedings of IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1994, pp. 425-428.
  102. H. Kriplani, F. Najm, and I. N. Hajj, "Improved delay and current models for estimating maximum currents in CMOS VLSI circuits," Proceedings of IEEE International Symposium on Circuits and Systems, London, England, May 1994, pp. 1.435-1.438.
  103. W. T. Chuang and I. N. Hajj, "Delay and area optimization for compact placement by gate sizing and relocation," Proceedings of IEEE International Conference on Computer-Aided Design (ICCAD'94), Santa Clara, CA, November 1994, pp. 145-148.
  104. I. N. Hajj, "VLSI design for reliability and high-performance," First International Conference on Electronics, Circuits and Systems, Cairo, Egypt, December 19-22, 1994. (Invited)
  105. Y. Tian and I. N. Hajj, "Mixed-mode timing simulation for accurate CMOS bridging fault detection," Proceedings of IEEE Custom Integrated Circuits (CICC'95), San Jose, CA, June 1995, pp. 643-646.
  106. I. N. Hajj, "Simulation of VLSI circuits and systems for reliability estimation," 1995 European Simulation Multiconference, Prague, Czech Republic, June 1995, pp. 735-738. (Invited)
  107. F. N. Najm, S. Goel, and I. N. Hajj, "Power estimation in sequential circuits," Proceedings of ACM/IEEE Des. Automat. Conf. (DAC'95), San Francisco, CA, June 1995, pp. 635-640. (Nominated for a Best Paper Award)
  108. T. Lee and I. N. Hajj, "Test generation for current testing of bridging faults in CMOS VLSI circuits," Proceedings of IEEE 38th Midwest Symposium on Circuits and Systems, Rio de Janeiro, Brazil, August 1995, pp. 326-329.
  109. Y. Tian and I. N. Hajj, "MIX: a mixed-mode CMOS bridging fault simulator," Proceedings of European Conf. on Circuit Theory and Design, Istanbul, Turkey, August 1995, pp. 1043-1046.
  110. I. N. Hajj, "Computer-aided simulation of very large scale integrated circuits and systems," Proceedings of First LAAS International Conference on Computer Simulation, Beirut, Lebanon, September 1995, pp. 1-8. (Invited)
  111. T. Lee, I. N. Hajj, E. M. Rudnick, and J. H. Patel, "Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI Circuits," Proceedings of 14th IEEE VLSI Test Symposium, Princeton, NJ, April 28-May 1, 1996, pp. 456-462.
  112. T. H. Chen, I. N. Hajj, E. M. Rudnick, and J. H. Patel, "An efficient IDDQ test generation scheme for bridging faults in CMOS digital circuits," Proceedings of 1996 IEEE Int. Workshop on IDDQ Testing (IDDQ96), Washington, DC, October 24-25, 1996, pp. 74-78.
  113. G. Veneris and I. N. Hajj, "A fast algorithm for locating and correcting simple design errors in VLSI digital circuits," Proceedings of IEEE Seventh Great Lakes Symposium on VLSI (GLS-VLSI'97), Urbana, IL, March 13-15, 1997, pp. 45-50.
  114. V. Saxena, F. N. Najm, and I. N. Hajj, "Monte-Carlo approach for power estimation in sequential circuits," Proceedings of European Design and Test Conference and Exhibition, Paris, France, March 17-20, 1997.
  115. T. H. Chen and I. N. Hajj, "A hierarchical bridging fault extraction approach for VLSI circuit layouts," Proceedings of IEEE International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, R.O.C., June 3-5, 1997, pp. 348-354.
  116. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "Analytical estimation of transition activity from word-level signal statistics," Proceedings of 34th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, June 9-13, 1997, pp. 582-587.
  117. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "Analytical estimation of transition activity for DSP architectures," Proceedings of IEEE International Symposium on Circuits and Systems, Hong Kong, June 9-13, 1997, pp. 1512-1515.
  118. S. Bobba and I. N. Hajj, "Estimation of maximum switching activity in digital VLSI circuits," Proceedings of IEEE 40th Midwest Symposium On Circuits and Systems (MWSCAS), Sacramento, CA, August 3-6, 1997, pp. 1130-1133.
  119. G. Veneris and I. N. Hajj. "Error diagnosis and correction in VLSI digital circuits," Proceedings of IEEE Midwest Symposium on VLSI Systems, Sacramento, CA, August 1997, pp. 1005-1008.
  120. T. H. Chen and I. N. Hajj, "Extraction, simulation, and testing of bridging faults in digital VLSI circuits," Proceedings of European Conference on Circuit Theory and Design (ECCTD'97), Budapest, Hungary, August 31-September 3, 1997, pp. 389-395.
  121. I. N. Hajj, "Utilizing the WEB in developing and teaching simulation methods," Proceedings of the Second IAAS International Conference on Computer Simulation, Beirut, Lebanon, September 1-4, 1997. (Invited)
  122. I. N. Hajj, "Reliability and power estimation of deep submicron VLSI circuits," Proceedings of 5th International Conference on VLSI and CAD, Seoul, Korea, October 1997. (Invited)
  123. T. Chen and I. Hajj, "GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment," Proceedings of IEEE/ACM Int. Conf. on Computer-Aided Design (ICCAD), San Jose, CA, November 1997, pp. 555-561.
  124. T. Chen and I. Hajj, "A hybrid (Logic+IDDQ) testing strategy using an iterative bridging fault filtering scheme," Proceedings of IEEE International Workshop on IDDQ Testing, Washington, DC, November 1997, pp. 63-67.
  125. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "Achievable bounds on signal transition activity," Proceedings of IEEE International Conference on Computer-Aided Design, San Jose, CA, November 9-13, 1997, pp. 126-129.
  126. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "Coding for low-power address and data busses: a source-coding framework and applications," Proceedings of 11th International Conference on VLSI Design, Chennai, India, January 5-9, 1998, pp. 18-23.
  127. N. Lu and I. N. Hajj, "Error estimation of reduced-order modeling of high speed RLCG circuits," Proceedings of IEEE Symposium on IC Package Design Integration, Santa Cruz, CA, February 2-3, 1998, pp. 143-148.
  128. S. Bobba and I. N. Hajj, "Maximum current estimation in programmable logic arrays," Proceedings of IEEE Great Lakes Symposium on VLSI (GLS'98), Lafayette, LA, February 1998, pp. 301-306. (Best Student Paper Award)
  129. S. Bobba and I. N. Hajj, "Estimation of maximum current envelope for power bus analysis and design," Proceedings of IEEE International Symposium On Physical Design (ISPD98), Monterey, CA, April 1998, pp. 141-146.
  130. S. Bobba, I. N. Hajj and N. R. Shanbhag, "Analytical expressions for average bit statistics of signal lines in DSP architectures," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'98), Vol. 6, Monterey, CA, June 1998, pp. 33-36.
  131. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "Signal coding for low power: fundamental limits and practical realizations," Proceedings Of IEEE International Symposium on Circuits and Systems (ISCAS'98), Vol. 2, Monterey, CA, June 1998, pp. 1-4.
  132. N. Bellas, I. N. Hajj, and C. Polychronopoulos, "A new scheme for I-cache energy reduction in high-performance processors," Proceedings Of Power-Driven Microarchitecture Workshop, Barcelona, Spain, June 1998, pp. 50-54.
  133. N. Bellas, I. N. Hajj, C. Polychronopoulos, and G. Stamoulis, "Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors," Proceedings of IEEE International Symposium on Low Power Electronic Design (ISLPED'98), Monterey, CA, August 1998, pp. 70-75.
  134. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "Decorrelating transformations for low-power adaptive filters," Proceedings of IEEE International Symposium on Low Power Electronics and Design, Monterey, CA, August 1998, pp. 250-255.
  135. N. Bellas, I. N. Hajj, C. Polychronopoulos, and G. Stamoulis, "Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors," Proceedings of IEEE International Symposium on Low Power Electronic Design (ISLPED'98), Monterey, CA, August 1998, pp. 70-75.
  136. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "Decorrelating transformations for low-power adaptive filters," Proceedings of IEEE International Symposium on Low Power Electronics and Design, Monterey, CA, August 1998, pp. 250-255.
  137. S. Bobba and I. N. Hajj, "Estimation of maximum voltage drop in the power bus of VLSI circuits," TECHCON'98, Las Vegas, NV, September 1998.
  138. N. Lu and I. N. Hajj, "Time-domain error analysis of reduced-order modeling of RLCG interconnects," TECHCON'98, Las Vegas, NV, September, 1998.
  139. S. Bobba, I. N. Hajj, and N. R. Shanbhag, "Analytical expressions for power dissipation of macro-blocks in DSP architectures," Proceedings of IEEE 12th International Conference on VLSI Design, (VLSI'99), Goa, India, January 1999, pp. 358-363.
  140. S. Bobba and I. N. Hajj, "Maximum leakage power estimation for CMOS circuits," Proceedings of IEEE Alessandro Volta Memorial International Workshop on Low Power Design (VOLTA'99), Como, Italy, March 4-5, 1999, pp. 116-124.
  141. N. Lu and I. Hajj, "An exact analytical time-domain model of distributed RC interconnects for high speed nonlinear circuit application," Proceedings of IEEE 9th Great Lakes Symposium on VLSI, Ann Arbor, MI, March\04-6, 1999, pp. 68-71.
  142. S. Bobba and I. N. Hajj, "Simultaneous switching noise in CMOS VLSI circuits," Proceedings of IEEE Southwest Symposium on Mixed-Signal Design, Tucson, AZ, April 11-13, 1999, pp. 15-20. (Best Paper Award)
  143. G. Veneris, S. Venkatraman, I. N. Hajj, and W. K. Fuchs, "Multiple design error diagnosis and correction in digital VLSI circuits," Proceedings of IEEE International VLSI Test Symposium (VTS'99), Dana Point, CA, April 25-29, 1999, pp. 58-63.
  144. G. Veneris and I. N. Hajj, "Correcting multiple design errors in digital VLSI circuits," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'99), Orlando, FL, May 30-June 2, 1999.
  145. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "Low-power distributed arithmetic architectures using non-uniform memory partitioning," Proceedings of IEEE International Symposium on Circuits and Systems, Orlando, FL, May 30-June 2, 1999.
  146. N. Lu and I. N. Hajj, "A reduced-order scheme for coupled lumped-distributed interconnect simulation," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'99), Orlando, FL, May 30-June 2, 1999.
  147. N. Bellas, I. N. Hajj, and C. Polychronopoulos, "A detailed, transistor-level energy model for SRAM-based caches," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'99), Orlando, FL, May 30-June 2, 1999.
  148. S. Ramprasad, I. N. Hajj, and F. N. Najm, "An optimization technique for dual-output domino logic," Proceedings of IEEE International Symposium on Low Power Electronics and Design, San Diego, CA, August 1999, pp. 258-260.
  149. N. Bellas, I. N. Hajj, and C. Polychronopoulos, "Using dynamic cache management techniques to reduce energy in a high-performance microprocessor," Proceedings of IEEE International Symposium on Low Power Electronics and Design, San Diego, CA, August 1999, pp. 64-69.
  150. Veneris and I. Hajj, "A hybrid approach to multiple design error detection and correction in digital VLSI circuits," Proceedings of IEEE International Conference on Electronic Circuits and Systems (ICECS'99), Pafos, Cyprus, September 5-8, 1999, pp. 347-350.
  151. S. Bobba and I. N. Hajj, "Design of dynamic circuits with enhanced noise tolerance," 1999 12th Annual IEEE International ASIC/SOC Conference, Washington DC, September 15-18, 1999, pp. 54-58.
  152. N. Bellas, I. N. Hajj, and C. Polychronopoulos, "Energy and performance improvements using a loop cache," IEEE International Conference on Computer Design, Austin, TX, October 10-13, 1999.
  153. S. Bobba and I. N. Hajj, "High-performance bidirectional repeaters," 10th Great Lakes Symposium on VLSI, Evanston, IL, March 2-4, 2000, pp. 53-58.
  154. Veneris, M. S. Abadir, and I. N. Hajj, "Design optimization with simulation-based diagnosis techniques," 1st IEEE Latin-American Test Workshop, Rio de Janeiro, Brazil, March 13-15, 2000.
  155. M. Becer and I. N. Hajj, "An analytical model for delay and crosstalk estimation with application to decoupling," IEEE International Symposium on Quality of Electronic Design (ISQED'2000), San Jose, CA, March 2000, pp. 51-57.
  156. G. Bai, S. Bobba, and I. N. Hajj, "Power bus maximum voltage drop in digital VLSI circuits," IEEE International Symposium On Quality of Electronic Design (ISQED'2000), San Jose, CA, March 2000, pp. 263-268.
  157. S. Bobba and I. N. Hajj, "Peak current estimation for digital filters," IEEE International Conference on Acoustics, Speech, and Signal Processing, Istanbul, Turkey, June 5-9, 2000.
  158. S. Bobba and I. N. Hajj, "Current mode threshold logic gates," IEEE International Conference on Computer Design (ICCD 2000), Austin, TX, September 17-20, 2000, pp. 235-240.
  159. G. Bai, S. Bobba, and I. N. Hajj, "Simulation and optimization of power distribution network in VLSI circuits," IEEE International Conference on Computer-Aided Design (ICCAD 2000), San Jose, CA, November 2000, pp.481-486
  160. M. Becer and I. N. Hajj, "An analytical model for delay and crosstalk estimation in interconnects under general switching conditions," IEEE International Conference on Electronic Circuits and Systems (ICECS'2000), Beirut, Lebanon, December 2000,pp.831-834, Vol.2
  161. N. Lu and I. N.Hajj, "A hierarchical based approach for coupling aware delay analysis of combinational logic blocks," IEEE International Conference on Electronic Circuits and Systems (ICECS'2000), Beirut, Lebanon, December 2000, 1012-1015, Vol. 2.
  162. M. M. Mansour, I. N. Hajj, and N. Shanbhag, "Instruction scheduling for low power on dynamically variable voltage processors," IEEE International Conference on Electronic Circuits and Systems (ICECS'2000), Beirut, Lebanon, December 2000, pp.613-618, Vol. 1.
  163. G. Bai, S. Bobba and I. N. Hajj, "Maximum power supply noise estimation in VLSI circuits using multimodal generic algorithms," IEEE International Conference on Electronics, Circuits and Systems, Malta, September 2001, pp. 1437-1440, Vol. 3.
  164. S. Bobba and I. N. Hajj, "Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits," IEEE Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australia, May 2001, pp. 195-198, Vol. 5.
  165. M. R. Becer, D. Blaauw, S. Sirichotiyakul, R. Levy, C. Oh, V. Zolotov, J. Zuo and I. N. Hajj, "A global driver sizing tool for functional crosstalk noise avoidance," IEEE International Symposium on Quality Electronic design, San Jose, CA, March 2001, pp.158-163.
  166. G. Bai, S. Bobba and I. N. Hajj, "RC power bus maximum voltage drop in digital VLSI circuits," IEEE International Symposium on Quality Electronic Design, San Jose, CA, March 2001, pp.205-210.
  167. Ninglong Lu and I. N. Hajj, "A fast coupling aware delay estimation scheme based on simplified circuit model," IEEE International Symposium on Quality Electronic Design, San Jose, CA, March 2001, pp.133-138.
  168. S. Bobba and I. N. Hajj, "Input Vector Generation for Maximum Intrinsic Decoupling Capacitance of VLSI Circuits" International Symposium on Circuits and Systems (ISCAS2001), Sydney, Australia, May 6-10, 2001, pp. 195-198, Vol. 5
  169. G. Bai, S. Bobba, and I. N. Hajj, "Static Timing Analysis Including Power Supply Noise effect on Propagation delay in VLSI Circuits," ACM/IEEE 38th Design Automation Conference, Las Vegas, Nevada, June 18-22, 2001
  170. G. Bai, S. Bobba, and I.N. Hajj, "Maximum Power Supply Noise Estimation in Digital VLSI Circuits Using Multimodal Genetic Algorithms" The 8th IEEE International Conference on Circuits and Systems (ICECS01), Malta, September 2001, pp. 1437-1440, Vol. 3
  171. S. Bobba and I. N. Hajj, "Maximum voltage variation in the power distribution network of VLSI circuits with RLC models," IEEE International Symposium on Low Power Electronics and Design, August 2001, pp. 376-381.
  172. M. R. Becer, D. Blaauw, P. Panda and I. N. Hajj, "Pre-route noise estimation in deep submicron integrated circuits," IEEE International Symposium on Quality Electronic Design, San Jose, CA, March 2002, pp. 413-418.
  173. G. Bai and I. N. Hajj, "Simultaneous switching noise and resonance analysis of on-chip power distribution network," IEEE International Symposium on Quality Electronic Design, San Jose, CA, March 2002, pp. 163-168.
  174. M. R. Becer, D. Blaauw, P. Panda and I. N. Hajj, "Analysis of noise avoidance techniques in DSM interconnects using a complete crosstalk noise model," Design automation and Test in Europe and Exhibition, Paris, France, March 2002, pp. 456-463.
  175. M. R. Becer, D. Blaauw, I. Algor, R. Panda, C. Oh, V. Zolotov and I. N. Hajj, "Post-route gate sizing for crosstalk noise reduction," IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2003, pp. 171-176, and Design Automation Conference (DAC), June 2003, pp.954-957.